Clock recovery is defined to be the reconstruction of timing information from digital data over packet switched networks. A packet switched network comprises various interfaces and layer protocols, whereas clock synchronization is usually maintained between physical connected interfaces and not maintained end-to-end. Hence, an accurate clock mechanism must be provided for services that require end-to-end clock synchronization (e.g. CES, Voice, Video, etc.) as well as for an end-to-end transmission of accurate timing information (e.g. cellular 3G applications).
The clock recovery mechanism over packet switched networks involves two basic procedures—generation of packets at the local site and reconstruction of the clock signal at the remote side. The first procedure generates packets carrying relevant information of the source clock (at the local side). These packets are transmitted to the remote side over the packet switched network. At the second procedure, reconstruction of the clock signal is obtained from the received information at the remote side.
A major problem in trying to synchronize a clock over an asynchronous network while achieving a high precision clock accuracy is to compensate for delay variation (e.g. filter out network jitter affecting arriving packets, latency changes, etc.). The delay in the network is a superposition of passive and active network factors. Passive network factors, such as fiber and cable, are usually constant physical factors, wherein their variation is very small and therefore can be neglected. However, active network factors, such as switches and routers, produce delay with significant variation that must be filtered out.
The traditional approach to filter out network jitter calculates the average delay using statistical estimation. However, the main drawback of this approach is that the statistical estimation depends on active network utilization factors, consequentially presenting unstable average delay calculations.
U.S. Pat. No. 6,363,073 discloses a circuit and method for synchronizing a service clock at a destination node with a service clock at a source node for circuit emulation service over a packet network. The method includes receiving data packets from a source node of the destination node. At the destination node, the method removes from the data packets residual time-stamp (RTS) values that were created at the source node based on information received from the service clock at the source node. RTS values are stored in memory at the destination node. The method determines a majority count and a minority count of RTS values over a period of time from the RTS values stored in memory. The method further uses the majority and minority counts to set the frequency of a service clock at the destination node for use in receiving data packets.
Yet another method for overcoming delay variation provides an adaptive clock, in which the receiver buffers incoming traffic and compares the level of the buffer with a local clock. The level of the buffer is used to control the frequency of the clock, so that the clock controlling the destination node buffer must operate at a frequency precisely matched to that of the service signal input at the source node in order to avoid buffer overflow or underflow and resulting loss of data. However, this method suffers from significant limitations revealing inaccurate results, and is therefore less efficient.
The prior art using such a method for clock recovery in a packet network include U.S. Pat. No. 6,721,328 to Nichols et al. and U.S. Pat. No. 6,400,683 to Jay. This method is further disclosed in U.S. Pat. No. 6,363,073 to Nichols.
The above-mentioned approaches for clock recovery all suffer from drawbacks which in one way or the other affect the final results.
Our previous invention (US Patent Application 2006/0291479) overcomes the disadvantages of prior art techniques by disclosing an improved and efficient system and method for reconstruction of the clock having the same frequency, over a packet switched network.
Such a system and method are provided for achieving high precision clock recovery by utilizing a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter.
However, in our previous invention the system uses a static threshold, i.e., the latency change mechanism checks if the latency changed by more than a static defined threshold, and if the latency has changed, the algorithm corrects all the minimum samples by the size of the latency change.
Such a system, however, cannot adapt itself for different network conditions with different packet delay variations.